程式扎記: [ Verilog Tutorial ] Common Combinational Components : 4x1 MUX

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2013年10月21日 星期一

[ Verilog Tutorial ] Common Combinational Components : 4x1 MUX

來源自 這裡
Equation:


Example:
  1. // mux_4t4.v  
  2.   
  3. // 4t4 MUX  
  4.   
  5. // ------------------------------------------------------------------  
  6. // Copyright (c) 2006 Susan Lysecky, University of Arizona  
  7. // Permission to copy is granted provided that this header remains  
  8. // intact. This software is provided with no warranties.  
  9. // ------------------------------------------------------------------  
  10.   
  11. // 4 data inputs (4 bits), and 1 output.  Select inputs determine  
  12. // which data input passes through to the output  
  13.   
  14. // Truth table for 4x1 MUX  
  15. // S1  S0  | D  
  16. // --------+-------  
  17. //  0   0  | input0  
  18. //  0   1  | input1  
  19. //  1   0  | input2  
  20. //  1   1  | input3  
  21.   
  22. `timescale 1ns / 1ns  
  23.   
  24. module Mux4t4(Input0, Input1, Input2, Input3, Sel, Data_out);  
  25.   
  26.    input [3:0] Input0;  
  27.    input [3:0] Input1;  
  28.    input [3:0] Input2;     
  29.    input [3:0] Input3;  
  30.    input [1:0] Sel;  
  31.    output [3:0] Data_out;  
  32.    reg [3:0] Data_out;  
  33.   
  34.    // constant declaration  
  35.    parameter S0 = 2'b00;  
  36.    parameter S1 = 2'b01;  
  37.    parameter S2 = 2'b10;  
  38.    parameter S3 = 2'b11;  
  39.   
  40.    always @ (Sel or Input0 or Input1 or Input2 or Input3)  
  41.    begin  
  42.       case(Sel)  
  43.          S0: begin  
  44.             Data_out <= Input0;  
  45.          end  
  46.          S1: begin  
  47.             Data_out <= Input1;  
  48.          end  
  49.          S2: begin  
  50.             Data_out <= Input2;  
  51.          end  
  52.          S3: begin  
  53.             Data_out <= Input3;  
  54.          end  
  55.       endcase  
  56.    end  
  57. endmodule  
Testbench:
  1. // mux4t4_tb.v  
  2.   
  3. // 4t4 MUX  
  4.   
  5. // ------------------------------------------------------------------  
  6. // Copyright (c) 2006 Susan Lysecky, University of Arizona  
  7. // Permission to copy is granted provided that this header remains  
  8. // intact. This software is provided with no warranties.  
  9. // ------------------------------------------------------------------  
  10.   
  11. `timescale 1ns / 1ns  
  12.   
  13. module Mux4t4TB;  
  14.   
  15.    reg [3:0] Input0_t, Input1_t, Input2_t, Input3_t;  
  16.    reg [2:0] Sel_t;  
  17.    wire [3:0] Data_out_t;   
  18.   
  19.    // module Mux4t4(Input0, Input1, Input2, Input3, Sel, Data_out);  
  20.    Mux4t4 Mux_1(Input0_t, Input1_t, Input2_t, Input3_t, Sel_t, Data_out_t);  
  21.      
  22.    initial  
  23.    begin  
  24.   
  25.       // assign values to input register  
  26.       Input0_t <= 0;  
  27.       Input1_t <= 1;  
  28.       Input2_t <= 2;  
  29.       Input3_t <= 3;  
  30.   
  31.       //case 0 - Input0 value should be display on output  
  32.       Sel_t <= 0;  
  33.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  34.         
  35.       //case 1 - Input1 value should be display on output  
  36.       Sel_t <= 1;  
  37.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  38.   
  39.       //case 2 - Input2 value should be display on output  
  40.       Sel_t <= 2;  
  41.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  42.   
  43.       //case 3 - Input3 value should be display on output  
  44.       Sel_t <= 3;  
  45.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  46.   
  47.       // reassign value to input register Input0 and display on output  
  48.       Input0_t = 8;  
  49.       Sel_t <= 0;  
  50.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  51.   
  52.       // reassign value to input register Input0 and display on output  
  53.       Input0_t = 4;  
  54.       Sel_t <= 0;  
  55.       #10 $display("S=%b; Data_out_t = %b", Sel_t, Data_out_t);  
  56.           
  57.    end  
  58. endmodule  
Simulation:


Console 輸出:
# S=000; Data_out_t = 0000
# S=001; Data_out_t = 0001
# S=010; Data_out_t = 0010
# S=011; Data_out_t = 0011
# S=000; Data_out_t = 1000
# S=000; Data_out_t = 0100


Supplement:
4x1 Multiplexer
A multiplexer or mux is a combinational circuits that selects several analog or digital input signals and forwards the selected input into a single output line...


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