[ Verilog Tutorial ] Common Combinational Components : Full 2-bit Adder

Equation: 
 

Example: 

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1. module Full_Adder(x, y, ci, sum, co);  
2.   input x, y, ci;  
3.   output sum, co;  
4.     
5.   assign {co, sum} = x + y + ci;  
6. endmodule  
7.   
8. module Full_Adder2(x, y, ci, sum, co);  
9.   input   [1:0] x, y;  
10.   input   ci;  
11.   output  [1:0] sum;  
12.   output  co;  
13.   wire    co_t;  
14.   Full_Adder fa1(x[0], y[0], ci, sum[0], co_t);  
15.   Full_Adder fa2(x[1], y[1], co_t, sum[1], co);  
16. endmodule  

Testbench: 

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1. `timescale 1ns / 1ns  
2.   
3. module Adder2TB;  
4.   reg   [1:0] A_t;  
5.   reg   [1:0] B_t;  
6.   wire  [1:0] R_t;  
7.   reg   CI_t;  
8.   wire  CO_t;  
9.     
10.   // module Full_Adder2(x, y, ci, sum, co);  
11.   Full_Adder2 fa2(.x(A_t),  
12.                   .y(B_t),  
13.                   .ci(CI_t),  
14.                   .sum(R_t),  
15.                   .co(CO_t));  
16.     
17.   initial  
18.     begin   
19.       CI_t = 0;   
20.       //case 0  
21.       A_t <= 0; B_t <= 0;  
22.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
23.   
24.       //case 1  
25.       A_t <= 1; B_t <= 0;  
26.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
27.         
28.       //case 2  
29.       A_t <= 1; B_t <= 1;  
30.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
31.         
32.       //case 3  
33.       A_t <= 2; B_t <= 1;  
34.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
35.         
36.       CI_t = 1;   
37.       //case 4  
38.       A_t <= 0; B_t <= 0;  
39.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
40.   
41.       //case 5  
42.       A_t <= 1; B_t <= 0;  
43.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
44.         
45.       //case 6  
46.       A_t <= 1; B_t <= 1;  
47.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
48.         
49.       //case 7  
50.       A_t <= 2; B_t <= 1;  
51.       #10 $display("A=%b; B=%b; CI=%b; Result=%b; CO=%b", A_t, B_t, CI_t, R_t, CO_t);  
52.     end  
53. endmodule  

Simulation: 
 

Console 輸出: 

# A=00; B=00; CI=0; Result=00; CO=0
# A=01; B=00; CI=0; Result=01; CO=0
# A=01; B=01; CI=0; Result=10; CO=0
# A=10; B=01; CI=0; Result=11; CO=0
# A=00; B=00; CI=1; Result=01; CO=0
# A=01; B=00; CI=1; Result=10; CO=0
# A=01; B=01; CI=1; Result=11; CO=0
# A=10; B=01; CI=1; Result=00; CO=1

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